Parametric yield estimation for a MOSFET integrated circuit

Author

Berrah, C.M.

Author_Institution

Dept. of Electr. Eng., Imperial Coll., London, UK

fYear

1990

fDate

1-3 May 1990

Firstpage

2260

Abstract

A method of estimating the parametric yield of a MOSFET integrated circuit using a piecewise-linear approximation to the yield body is presented. First results show that the method is useful in estimating yield as well as predicting the performance of both analog and digital MOSFET circuits. The statistical changes that are considered are the geometrical ones (as they are often the most important), together with the oxide capacitance and the flat band voltage, which have been proven to fully describe the variation in behavior of MOSFET circuits; the other parameters have a smaller influence and have been neglected for simplicity

Keywords

MOS integrated circuits; integrated circuit technology; parameter estimation; piecewise-linear techniques; statistical analysis; MOSFET integrated circuit; analogue circuits; digital circuits; flat band voltage; oxide capacitance; parametric yield estimation; piecewise-linear approximation; Capacitance; Educational institutions; Equations; Integrated circuit technology; Integrated circuit yield; MOSFET circuits; Piecewise linear approximation; Piecewise linear techniques; Voltage; Yield estimation;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.112458

Filename

112458