VLSI circuits for decomposing binary integers into signed power-of-two terms

If the coefficients of a digital filter are approximated by the sum of signed power-of-two terms, there will be a significant reduction in the area used and an improvement in the speed of custom implementations at the expense of a slight frequency-response deterioration. The authors present two circuits for extracting from a given integer a prescribed number of signed power-of-two terms whose sum is the closest approximation to that given integer. One of these circuits is bit-serial and the other is bit-parallel. Example layouts in a CMOS process are given