• DocumentCode
    2661555
  • Title

    Isolated Preset Architecture for a 32nm SOI embedded DRAM macro

  • Author

    Barth, John ; Plass, Don ; Vehabovic, Adis ; Joshi, Rajiv ; Kanj, Rouwaida ; Burns, Steve ; Weaver, Todd

  • Author_Institution
    Syst. & Technol. Group, IBM, Hopewell Junction, NY, USA
  • fYear
    2012
  • fDate
    13-15 June 2012
  • Firstpage
    110
  • Lastpage
    111
  • Abstract
    The Isolated Preset Architecture (IPA) improves retention characteristics by implementing a weak read `1´ Isolation scheme, allowing a lower stored `1´ level to be sensed. The architecture also reduces sub-array area by 15% and bit-line activation power by 2× compared to previous design, without impacting performance. The architecture was implemented in IBM´s 32nm High-K/Metal SOI embedded DRAM technology. Hardware results confirm 1.8ns random cycle and 2× improved retention characteristic with optimized Analog reference tuning.
  • Keywords
    DRAM chips; high-k dielectric thin films; silicon-on-insulator; IPA; high-k-metal SOI embedded DRAM technology; isolated preset architecture; optimized analog reference tuning; retention characteristic; size 32 nm; time 1.8 ns; Computer architecture; Hardware; Inverters; Isolators; Microprocessors; Random access memory; Sensors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2012 Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4673-0848-9
  • Electronic_ISBN
    978-1-4673-0845-8
  • Type

    conf

  • DOI
    10.1109/VLSIC.2012.6243814
  • Filename
    6243814
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2661555