Benchmark results for high-speed 4-bit accumulators implemented in indium phosphide DHBT technology

High-speed accumulators are frequently used as a benchmark of the high-speed performance and ability to yield large scale circuits in InP double heterojunction bipolar (DHBT) processes. In previous work, we reported test results of an InP DHBT 4-bit accumulator with 624 transistors operating at 41 GHz clock frequency with a power consumption of 4.1W. In this work, we report on modifications that allow the circuit to operate at a lower supply voltage and a corresponding lower power consumption. Simulation results for this modification indicate that a 16% power reduction can be obtained, while maintaining a high-speed operating frequency of 40 GHz.