Systolic and parallel realization of 2-D IIR digital filters

Author

Kwan, H.K.

Author_Institution

Dept. of Electr. Eng., Windsor Univ., Ont., Canada

fYear

1990

fDate

1-3 May 1990

Firstpage

2345

Abstract

A method for multi-input and multi-output systolic realization of 2-D infinite-impulse-response (IIR) digital filters is presented. The filter transfer functions under consideration are first-order and second-order, and also of orthogonal symmetry with separable denominator format. Because of its multi-input and multi-output systolic architecture, it is most suitable for high-speed processing of computationally intensive signals such as images. The method utilizes parallelism to speed up computation, providing a practical solution to real-time recursive digital filtering. The resultant architecture is regular and systolic and could be easily adapted for VLSI implementation

Keywords

filtering and prediction theory; parallel architectures; picture processing; systolic arrays; transfer functions; two-dimensional digital filters; 2D digital filters; IIR digital filters; VLSI implementation; computationally intensive signals; filter transfer functions; high-speed processing; image processing; infinite-impulse-response; multiinput/multioutput systolic realisation; orthogonal symmetry; parallel realization; real-time recursive digital filtering; separable denominator format; systolic architecture; Clocks; Computer architecture; Delay; Digital filters; Filtering; Finite impulse response filter; IIR filters; Nonlinear filters; Signal processing; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.112480

Filename

112480