• DocumentCode
    2661851
  • Title

    A 25-Gb/s 5-mWCMOS CDR/deserializer

  • Author

    Jung, Jun Won ; Razavi, Behzad

  • Author_Institution
    Electr. Eng. Dept., Univ. of California, Los Angeles, CA, USA
  • fYear
    2012
  • fDate
    13-15 June 2012
  • Firstpage
    138
  • Lastpage
    139
  • Abstract
    A half-rate clock and data recovery circuit and a deserializer employ charge-steering logic to reduce the power consumption. Realized in 65-nm technology, the overall circuit draws 5 mW from a 1-V supply, producing a clock with an rms jitter of 1.5 ps and a jitter tolerance of 0.5 UIpp at 5 MHz.
  • Keywords
    CMOS logic circuits; clock and data recovery circuits; jitter; CMOS CDR-deserializer; charge-steering logic; data recovery circuit; frequency 5 MHz; half-rate clock; jitter tolerance; power 5 mW; power consumption; size 65 nm; voltage 1 V; CMOS integrated circuits; Clocks; Jitter; Latches; Optical signal processing; Power demand; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2012 Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4673-0848-9
  • Electronic_ISBN
    978-1-4673-0845-8
  • Type

    conf

  • DOI
    10.1109/VLSIC.2012.6243828
  • Filename
    6243828
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2661851