Indentification of viable paths using binary decision diagrams

An efficient algorithm for the indentification of viable paths in a combinational logic circuit using binary decision diagrams is described. The viable paths are justified by generating and resolving logic and delay constraints along the critical path based on the stable times and stable values of the side inputs. Results of the analysis, using the ISCAS combinational benchmark circuits, indicate that most of the circuits can be analyzed in a few CPU-seconds