A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications

Author

Hui Xu ; Tanabe, Jun ; Usui, Hideyuki ; Hosoda, S. ; Sano, Tomomi ; Yamamoto, Koji ; Kodaka, T. ; Nonogaki, N. ; Ozaki, N. ; Miyamori, Takashi

Author_Institution

Toshiba Semicond. & Storage Products Co., Toshiba Corp., Kawasaki, Japan

fYear

2012

fDate

13-15 June 2012

Firstpage

150

Lastpage

151

Abstract

A low-power many-core SoC for multimedia applications is implemented in 40nm CMOS technology. Within a 210mm² die, two 32-core clusters are integrated with dynamically reconfigurable processors, hardware accelerators, 2-channel DDR3 I/Fs, and other peripherals. Processor cores in the cluster share a 2MB L2 cache connected through a tree-based Network-on-Chip (NoC). The high scalability and low power consumption are accomplished by parallelized firmware for multimedia applications, such as the H.264 1080p 30fps decoding under 500mW and the super resolution 4K2K 15fps image processing under 800mW.

Keywords

CMOS integrated circuits; cache storage; firmware; low-power electronics; multimedia communication; network-on-chip; CMOS technology; H.264 decoding; L2 cache; dynamically reconfigurable processors; hardware accelerators; low power many-core SoC; multimedia applications; network-on-chip; parallelized firmware; power 500 mW; power 800 mW; processor cores; size 40 nm; storage capacity 2 Mbit; super resolution 4K2K image processing; tree based NoC; two-channel DDR3 I/F; Computer architecture; Decoding; Hardware; Multimedia communication; Program processors; Synchronization; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2012 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4673-0848-9

Electronic_ISBN

978-1-4673-0845-8

Type

conf

DOI

10.1109/VLSIC.2012.6243834

Filename

6243834