Networking on chip with platform FPGAs

Author

Brebner, Gordon ; Levi, Delon

Author_Institution

Xilinx Res. Lab., Xilinx Inc., San Jose, CA, USA

fYear

2003

fDate

15-17 Dec. 2003

Firstpage

13

Lastpage

20

Abstract

This paper is concerned with networking at the chip level. Networks on chip have become a convenient focus for discussing the architecture of systems on chip, and design methodologies for such systems. One central question for such a focus concerns the extent to which it is useful or realistic just to scale down approaches used conventionally in larger-area computer networking. Here, we discuss this question, in the context of the modern Platform FPGA device as a system on chip substrate. We illustrate the discussion with two design examples of networking on chip being implemented in an unconventional way.

Keywords

field programmable gate arrays; reconfigurable architectures; substrates; system-on-chip; wide area networks; computer networking; design methodologies; field programmable gate arrays; networking on chip; platform FPGA device; platform FPGAs; system on chip substrate; Application specific integrated circuits; Computer networks; Concurrent computing; Distributed computing; Field programmable gate arrays; Integrated circuit interconnections; Internet; Logic; Network-on-a-chip; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on

Print_ISBN

0-7803-8320-6

Type

conf

DOI

10.1109/FPT.2003.1275726

Filename

1275726