• DocumentCode
    2662097
  • Title

    Improved SVD systolic array and implementation on FPGA

  • Author

    Ahmedsaid, A. ; Amira, A. ; Bouridane, A.

  • Author_Institution
    Sch. of Comput. Sci., Queen´´s Univ., Belfast, UK
  • fYear
    2003
  • fDate
    15-17 Dec. 2003
  • Firstpage
    35
  • Lastpage
    42
  • Abstract
    This paper presents an efficient systolic array for the computation of the Singular Value Decomposition (SVD). The proposed architecture is three times more efficient and faster than the Brent, Luk, Van Loan (BLV) SVD systolic array. The architecture has been implemented efficiently on FPGA using a high level language for hardware design "Handel-C".
  • Keywords
    field programmable gate arrays; hardware description languages; high level languages; singular value decomposition; systolic arrays; BLV array; Brent-Luk-Van Loan array; FPGA; Handel-C language; SVD systolic array; field programmable gate arrays; hardware design; high level language; singular value decomposition; Adaptive arrays; Computer architecture; Computer science; Field programmable gate arrays; Hardware; Image analysis; Jacobian matrices; Principal component analysis; Singular value decomposition; Systolic arrays;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on
  • Print_ISBN
    0-7803-8320-6
  • Type

    conf

  • DOI
    10.1109/FPT.2003.1275729
  • Filename
    1275729
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2662097