Analysis and compact modeling of a vertical grounded-base NPN bipolar transistor used as an ESD protection in a smart power technology

Author

Bertrand, G. ; Delage, C. ; Bafleur, M. ; Nolhier, N. ; Dorkel, J.M. ; Nguyen, Q. ; Mauran, N. ; Perdu, P.

Author_Institution

Lab. d´´Autom. et d´´Anal. des Syst., CNRS, Toulouse, France

fYear

2000

fDate

26-26 Sept. 2000

Firstpage

28

Lastpage

31

Abstract

A thorough analysis of the physical mechanisms involved in a vertical grounded-base NPN bipolar transistor (VGBNPN) under ESD stress is first carried out by 2D-device simulation, square pulse measurements (TLP) and photoemission experiments. As a result, we propose a compact model using a new physics-based avalanche formulation. This allows reproduction of the unexpected low value of the VGBNPN snapback holding voltage under TLP stress.

Keywords

CMOS integrated circuits; avalanche breakdown; bipolar transistors; electrostatic discharge; integrated circuit reliability; photoemission; power integrated circuits; protection; semiconductor device breakdown; semiconductor device measurement; semiconductor device models; 2D-device simulation; CMOS smart power technology; ESD protection; ESD stress; TLP square pulse measurements; TLP stress; VGBNPN; VGBNPN snapback holding voltage; modeling; photoemission experiments; physical mechanisms; physics-based avalanche model formulation; smart power technology; transmission line square pulse measurements; vertical grounded-base NPN bipolar transistor; Analytical models; Bipolar transistors; CMOS technology; Electrostatic discharge; Protection; Pulse measurements; Semiconductor device modeling; Stress; Transmission line measurements; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting, 2000. Proceedings of the 2000

Conference_Location

Minneapolis, MN, USA

ISSN

1088-9299

Print_ISBN

0-7803-6384-1

Type

conf

DOI

10.1109/BIPOL.2000.886167

Filename

886167