Modular exponentiation using parallel multipliers

Author

Tang, S.H. ; Tsui, K.S. ; Leong, P.H.W.

Author_Institution

Dept. of Comput. Sci. & Eng;, Chinese Univ. of Hong Kong, Shatin, China

fYear

2003

fDate

15-17 Dec. 2003

Firstpage

52

Lastpage

59

Abstract

A field programmable gate array (FPGA) semi-systolic implementation of a modular exponentiation unit, suitable for use in implementing the RSA public key cryptosystem is presented. The design is carefully matched with features of the FPGA architecture, utilizing embedded 18×18-bit multipliers on the FPGA and employing a carry save addition scheme. Using this architecture, a 1024-bit modular exponentiation can operate at 90 MHz on a Xilinx XC2V3000-6 device and perform a 1024-bit RSA decryption in 0.66 ms with the Chinese Remainder Theorem.

Keywords

embedded systems; field programmable gate arrays; public key cryptography; systolic arrays; 0.66 ms; 90 MHz; Chinese remainder theorem; FPGA; RSA decryption; RSA public key cryptosystem; Xilinx XC2V3000-6 device; carry save addition scheme; embedded bit multipliers; field programmable gate array; modular exponentiation; parallel multipliers; Application specific integrated circuits; Clocks; Computer architecture; Computer science; Field programmable gate arrays; Hardware; Parallel processing; Pipeline processing; Public key; Public key cryptography;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on

Print_ISBN

0-7803-8320-6

Type

conf

DOI

10.1109/FPT.2003.1275731

Filename

1275731