From recursive algorithm to parallel VLSI accelerator: a hierarchical design system with testbed

An instance of a design method allowing the interactive mapping of certain recursive algorithms to nearest-neighbor SMD (single-instruction, multiple data stream) processor arrays is considered. The design system accepts certain sequential iterative algorithms and aids the designer in obtaining any desired fixed size parallel or pipeline (VLSI) implementation. The authors give a concise description of a prototype design system that supports the mapping trajectory, including the VLSI design of the processor elements, as well as the testing of the functional behavior of both an individual processor and the processor array in a real-world environment. An illustrative example is given