A set of switch-level synthesis tools

A set of switch-level synthesis tools is described. First, a tool, called sea-of-devices (SOD), that accepts an arbitrary transistor-level schematic and produces a gate-matrix style layout on a virtual grid is presented. The output is run through a compactor that does technology binding (MACS). Because it is a true cell compiler, SOD does not make use of any library of predefined cells: each subcircuit is laid out from scratch each time the tool is run. This means that the system can accept any circuit, including ones with individually sized transistors, such as those produced by the TILOS transistor sizer. Typical runs of SOD are in the 50-5000 transistor range. A tool which provides an efficient way to specify transistor circuits not limited to libraries, called the Switch-Level IC Compiler (SLICC), is discussed. It translates a subset of C directly into transistors, again without using any library, SLIC understands local logic transformations and CMOS rules (e.g. complementary and pass logic). It is not a general logic optimizer, but can accept the output of such a tool. The pipeline of a design is followed through SLICC, TILOS, SOD, and MACS