A Low Power Asynchronous GPS Baseband Processor

Author

Tang, Benjamin Z. ; Longfield, Stephen, Jr. ; Bhave, Sunil A. ; Manohar, Rajjit

Author_Institution

Schoo l of Electricaland Comput. Eng., Cornell Univ., Ithaca, NY, USA

fYear

2012

fDate

7-9 May 2012

Firstpage

33

Lastpage

40

Abstract

We present the design and implementation of an asynchronous Global Positioning System (GPS) base band processor architecture designed with a combination of Quasi-Delay-Insensitive (QDI) and bundled-data techniques, with a focus on minimizing power consumption. All subsystems run at their natural frequency without clocking and all signal processing is done on-the-fly. Transistor-level simulations show that our system consumes only 1.4mW with position 3-D rms error below 4 meters, comparing favorably to other contemporary GPS base band processors.

Keywords

Global Positioning System; asynchronous circuits; low-power electronics; Global Positioning System; bundled-data techniques; low power asynchronous GPS baseband processor architecture; position 3D RMS error; power consumption; quasidelay-insensitive; signal processing; transistor-level simulations; Asynchronous circuits; Asynchronous Circuits; Bundled-Data; GPS; Low-Power Receiver; QDI;

fLanguage

English

Publisher

ieee

Conference_Titel

Asynchronous Circuits and Systems (ASYNC), 2012 18th IEEE International Symposium on

Conference_Location

Lyngby

ISSN

1522-8681

Print_ISBN

978-1-4673-1360-5

Type

conf

DOI

10.1109/ASYNC.2012.20

Filename

6243879