• DocumentCode
    2662812
  • Title

    ESD protection for BiCMOS circuits

  • Author

    Joshi, Sopan ; Juliano, Patrick ; Rosenbaum, Elyse ; Kaatz, Gary ; Kang, Sung-Mo

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    218
  • Lastpage
    221
  • Abstract
    We introduce two new ESD protection elements suitable for use in BiCMOS process technology-a grounded gate NMOS built inside a junction-isolated p-well which acts as a lateral NPN, and a modified Zener-triggered vertical NPN circuit
  • Keywords
    BiCMOS integrated circuits; MOSFET; Zener diodes; bipolar transistors; electrostatic discharge; integrated circuit measurement; integrated circuit reliability; isolation technology; protection; BJT; BiCMOS circuits; BiCMOS process technology; ESD protection; ESD protection elements; grounded gate NMOSFET; junction-isolated p-well; lateral NPN; modified Zener-triggered vertical NPN circuit; BiCMOS integrated circuits; Breakdown voltage; Electric breakdown; Electrostatic discharge; Isolation technology; MOS devices; Parasitic capacitance; Protection; Radio frequency; Resistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Bipolar/BiCMOS Circuits and Technology Meeting, 2000. Proceedings of the 2000
  • Conference_Location
    Minneapolis, MN
  • ISSN
    1088-9299
  • Print_ISBN
    0-7803-6384-1
  • Type

    conf

  • DOI
    10.1109/BIPOL.2000.886209
  • Filename
    886209
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2662812