Reconfigurable architecture for probabilistic neural network system

Author

Mizuno, Ryosuke ; Aibe, Noriyuki ; Yasunaga, Moritoshi ; Yoshihara, Ikuo

Author_Institution

Syst. & Inf. Eng., Tsukuba Univ., Japan

fYear

2003

fDate

15-17 Dec. 2003

Firstpage

367

Lastpage

370

Abstract

Reconfigurable architecture for the probabilistic neural network (PNN) is proposed and the PNN hardware system is developed using FPGAs. In the system, preprocessing circuits as well as the PNN can be reconfigured adapting each task. Potential performance of the PNN cannot be brought out until the total reconfigurability including the preprocessing is achieved. The developed system shows high recognition accuracy with high processing speed for some image recognition tasks.

Keywords

field programmable gate arrays; image recognition; neural nets; probabilistic logic; program processors; reconfigurable architectures; FPGA; PNN; PNN hardware system; field programmable gate arrays; image recognition; preprocessing circuits; probabilistic neural network; reconfigurable architecture; Counting circuits; Field programmable gate arrays; Image recognition; Kernel; Neural network hardware; Neural networks; Neurons; Reconfigurable architectures; Registers; Systems engineering and theory;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on

Print_ISBN

0-7803-8320-6

Type

conf

DOI

10.1109/FPT.2003.1275778

Filename

1275778

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2662815