Uncle - An RTL Approach to Asynchronous Design

Uncle (Unified NULL Convention Logic Environment) is an end-to-end toolset for creating asynchronous designs using NULL Convention Logic (NCL). Designs are specified in Verilog RTL, with the user responsible for specifying registers, data path elements, and finite state machines for controlling data path sequencing. A commercial synthesis tool is used to produce a gate-level net list of primitive logic gates and storage elements, which is then transformed into an NCL net list by the Uncle mapping flow. Performance optimizations supported by the flow are net buffering for target slew and delay balancing between latch stages. Both data-driven and control-driven (i.e. Balsa-style) schemes are supported. Transistor count, performance, and energy comparisons are made for Uncle versus Balsa-generated net lists for GCD and Viterbi decoder designs, with the Uncle designs comparing favorably in all three areas.