DocumentCode
2662874
Title
Partitioning logic to optimize routability on graph structures
Author
Vijayan, Gopalakrishnan
Author_Institution
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fYear
1990
fDate
1-3 May 1990
Firstpage
2638
Abstract
The problem of partitioning the nodes of a logic network (i.e. a hypergraph) on to the vertices of a partition graph G , in which the cost function to be minimized is the cost of global routing (i.e. the cost of routing the nets of the logic on the edges of the graph G ), is studied. Each vertex of the partition graph has a given upper bound on the number of nodes of the logic that can be assigned to the vertex. the nets of the logic network and the edges of the partition graph may have weights associated with them, which appear as multiplicative factors in the routing cost function. This partitioning program is called the min-cost partitioning on a graph (MCPG) problem. The MCPG model is very general and can be applied in many partitioning situations arising in VLSI physical design. Two such applications are described
Keywords
VLSI; graph theory; logic design; MCPG model; VLSI physical design; cost function; global routing; graph structures; hypergraph; logic network; min-cost partitioning on a graph; multiplicative factors; nodes; partition graph; partitioning; routability; routing cost function; upper bound; weights; Cost function; Delay; Ear; Linear programming; Logic design; Routing; Timing; Upper bound; Very large scale integration; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location
New Orleans, LA
Type
conf
DOI
10.1109/ISCAS.1990.112550
Filename
112550
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