Tiempo Asynchronous Circuits System Verilog Modeling Language

This paper describes the System Verilog modeling language developed by Tiempo to design asynchronous circuits. The language enables designers to model, verify and debug asynchronous circuits using standard simulators, viewers and debuggers. The paper first highlights how the concept of communication channel is supported and how System Verilog is used to declare channels and ports, reading and writing ports and testing port´s activity. The different memorization semantics associated with channels are addressed. Modeling and designing asynchronous circuit architectures using channels is then presented taking advantage of System Verilog modules and processes. The modeling of distributed and concurrent asynchronous circuits using the concepts defined in Tiempo System Verilog language is then described. An illustrative example shows the efficiency of the language as well as its ease-of-use.