Low-power implementation of H.324 audiovisual codec dedicated to mobile computing

Author

Onoye, Takao ; Fujita, Gen ; Okuhata, Hiroyuki ; Miki, Morgan H. ; Shirakawa, Isao

Author_Institution

Dept. Inf. Syst. Eng., Osaka Univ., Japan

fYear

1998

fDate

10-13 Feb 1998

Firstpage

589

Lastpage

594

Abstract

A VLSI implementation of the H.324 audiovisual codec is described. A number of sophisticated low-power architectures have been devised dedicatedly for the mobile use. A set of specific functional units, each corresponding to a process of H.263 video codec, is employed to lighten different performance bottlenecks. A compact DSP core composed of two MAC units is used for both ACELP and MP-MLQ coding schemes of the G.723.1 speech codec. The proposed audiovisual codec core has been implemented by using 0.35 μm CMOS 4LM technology, which contains totally 420 K transistors with the dissipation of 224.32 mW from single 3.3 V supply

Keywords

CMOS integrated circuits; VLSI; encoding; maximum likelihood decoding; speech codecs; video codecs; ACELP; CMOS 4LM technology; DSP core; G.723.1 speech codec; H.324 audiovisual codec; MAC units; MP-MLQ coding; VLSI implementation; functional units; low-power implementation; mobile computing; video codec; Bit rate; CMOS technology; Communication standards; Digital signal processing; Energy consumption; Mobile communication; Mobile computing; Speech codecs; Very large scale integration; Video codecs;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

0-7803-4425-1

Type

conf

DOI

10.1109/ASPDAC.1998.669566

Filename

669566