Compiling to FPGAs via an EPIC compiler´s intermediate representation

The increasing density and speed of modern field programmable gate arrays offer the reconfigurable systems using them greater capability and flexibility, in particular for more complex computation. However, there remains a very important problem of how to design on a more abstract level to manage the vast hardware resource and shorten the design time. This paper presents an approach to compile a system level description to hardware through a conventional software intermediate representation (IR) of a state-of-the-art optimizing compiler for Explicitly Parallel Instruction Computing (EPIC) processors. The front end compiles C programs into an intermediate representation for an infinite resource EPIC processor. The intermediate representation contains all the information of control flow graph of basic blocks. It is from this intermediate representation that we have devised means to generate synthesizable Register Transfer level (RTL-level) Verilog description that can be mapped into the reconfigurable HW device. We will describe the details of the translation process and the performance on actual FPGA hardware.