Self Synchronous Circuits for Error Robust Operation in Sub-100nm Processes

We have previously presented a process variation robust self synchronous FPGA that uses dual pipelines (DP) for high throughput 3GHz operation. As process technology shrinks, the importance of not only variation robust, but error robust systems increases. In this paper, we analyze the DP robustness to single-event-upsets and propose several gate-level architectures to implement error detection and correction, autonomous disabling of faulty pipeline-stages, and programmable time-interleaved redundancy, showing that self synchronous systems are a very promising candidate for addressing reliability problems in sub-100nm circuits. Test chips are fabricated and show successful operation, detection of errors, and autonomous pipeline-disabling in 65nm and 40nm.