Title :
The Multiplier Tree FIR filter architecture
Author :
Carreira, A. ; Fox, T.W.
Abstract :
The Multiplier Tree FIR filter architecture eliminates redundant arithmetic elements in the constant coefficient multipliers of the transposed form FIR filter architecture, facilitating low hardware cost filter implementations. This paper presents the Multiplier Tree FIR Filter architecture and implementation results for this architecture. A comparison of this architecture to previous FIR filter implementations is presented. Results for 95 and 45-tap FIR filter implementations show hardware cost can be reduced significantly with the Multiplier Tree architecture.
Keywords :
FIR filters; computer architecture; trees (mathematics); constant coefficient multipliers; hardware cost; hardware cost filter; multiplier tree FIR filter architecture; redundant arithmetic elements; Adders; Arithmetic; Costs; Digital filters; Energy consumption; Field programmable gate arrays; Finite impulse response filter; Hardware; Image processing; Radar imaging;
Conference_Titel :
Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on
Print_ISBN :
0-7803-8320-6
DOI :
10.1109/FPT.2003.1275799
