Title :
A top-down built-in self-test design in VLSI testing
Author :
Chen, Chien-In Henry
Author_Institution :
Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA
Abstract :
A top-down design of test generation and response analysis for built-in self-test (BIST) is proposed. The design procedure is computationally efficient for test generation, and produces test generation circuitry with low hardware overhead. The effectiveness of the approach is demonstrated by detailed comparisons of the results with those obtained with existing techniques. For response analysis, a delay redundancy check is proposed to improve the failure rate of a vertical and horizontal redundancy check fault-detection scheme. In combination with the two-signature scheme, the frequency of aliasing is reduced to one in 24n for an n-input, m-output circuit under test, where 2n>m
Keywords :
VLSI; built-in self test; integrated circuit testing; BIST; VLSI testing; computationally efficient; delay redundancy check; design procedure; fault analysis; fault coverage increase; frequency of aliasing reduction; low hardware overhead; response analysis; test generation circuitry; top-down built-in self-test design; top-down design of test generation; two-signature scheme; vertical and horizontal redundancy check fault-detection scheme; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Delay; Failure analysis; Frequency; Hardware; Redundancy; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112571
