FPGA Implementation of 2-D DCT Engine for Vision Based Tracking of Dynamic Obstacles

In this paper, we propose a novel architecture for implementation of a hardware accelerator for computation of two dimensional Discrete Cosine Transform (2-D DCT) for vision-based tracking of dynamic obstacles used in autonomous robot navigation. Real time motion estimation for tracking remains a challenge due to its large computational complexity. The main complexity in discrete cosine transform based motion estimation (DXT-ME) is the computation of 2-D DCT. Direct implementation of 2-D DCT involves N4 multiplications for an N x N image which is highly impractical to meet the needs of real time applications. The proposed architecture for implementation of 2-D DCT uses Look up tables (LUTs). They are used to store the pre-computed vector products of the input vector and the coefficient matrix of DCT that eliminates the need of multipliers completely. This makes the architecture highly time efficient. Besides this, the routing delay and power consumption is also reduced significantly by making the computations highly local and parallel. The paper also presents a comparison of the performance metrics of existing 2-D DCT architectures with the proposed architecture.