Title :
Digital phase-locked loop constructed by AND-filter
Author :
Inoue, Takashi ; Tokunaga, Manabu ; Mori, Shinsaku
Author_Institution :
Dept. of Electr. Eng., Keio Univ., Yokohama, Japan
Abstract :
A type of digital phase-locked loop (DPLL) with an AND-filter instead of a random walk filter (RWF) is proposed in order to increase phase acquisition speed. This loop is compared with conventional loops. It is found that the phase acquisition speed of this proposed loop is better than that of either of the conventional loops with the same noise suppression effect. Performance is verified by computer simulation
Keywords :
digital circuits; phase-locked loops; AND-filter; DPLL; computer simulation; digital PLL; noise suppression effect; phase acquisition speed; phase-locked loop; Clocks; Computer simulation; Filters; Magnetooptic recording; Phase locked loops; Phase noise; Phase shifters; Pulse generation; Shift registers; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112587
