DocumentCode
2663671
Title
Effective clock-feedthrough reduction in switched capacitor circuits
Author
Willingham, Scott D. ; Martin, Kenneth W.
Author_Institution
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
fYear
1990
fDate
1-3 May 1990
Firstpage
2821
Abstract
Techniques for the suppression of clock-feedthrough errors in CMOS switched capacitor circuits, such as differential, quasi-differential, and feedback-based suppression, are described. Example circuits are used to illustrate the techniques and to show how, in proper implementation, systematic errors can be avoided and maximum feedthrough suppression obtained. Simulation results to demonstrate the effectiveness of the described techniques are presented
Keywords
CMOS integrated circuits; feedback; linear integrated circuits; switched capacitor networks; CMOS; clock-feedthrough reduction; differential error suppression; feedback-based suppression; switched capacitor circuits; Circuit simulation; Circuit synthesis; Clocks; Differential amplifiers; Dynamic range; Frequency; Impedance; Operational amplifiers; Switched capacitor circuits; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location
New Orleans, LA
Type
conf
DOI
10.1109/ISCAS.1990.112597
Filename
112597
Link To Document