Title :
BTIarray: A Time-Overlapping Transistor Array for Efficient Statistical Characterization of Bias Temperature Instability
Author :
Awano, Hiromitsu ; Hiromoto, Masayuki ; Sato, Takao
Author_Institution :
Grad. Sch. of Inf., Kyoto Univ., Kyoto, Japan
Abstract :
A transistor array has been developed that is capable of efficiently collecting parametric data for a statistical model of bias-temperature instability (BTI) degradation. This BTIarray uses a time-overlapping technique, in which all transistors in the array undergo BTI stress or recovery bias in parallel, which greatly reduces the measurement time for a large number of transistors. An implementation using 65-nm technology validated the time-overlapping concept. The use of this array reduces the time to measure the statistical threshold voltage shifts of 128 transistors from a month to within a day while retaining precision as high as 50 μV (rms). Experiments showed that the statistical distribution of the time exponent for the degradation model of the pMOS transistor was log-normal.
Keywords :
MOSFET; statistical distributions; BTI recovery array; BTI stress array; BTIarray; bias-temperature instability degradation; pMOS transistor; parametric data collection; size 65 nm; statistical distribution; statistical threshold voltage shift measurement; time-overlapping transistor array; Degradation; Stress; Stress measurement; Threshold voltage; Time measurement; Transistors; Voltage measurement; Device aging; bias-temperature instability (BTI); device degradation; negative BTI (NBTI); positive BTI (PBTI); reliability;
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
DOI :
10.1109/TDMR.2014.2327164