Title :
Automatic signal processor code generation: matrix reduction based module optimization
Author :
Reichler, Thomas ; Hartimo, Iiro ; Jaatinen, Juhana
Author_Institution :
Lab. of Signal Process. & Comput. Technol., Helsinki Univ. of Technol., Espoo, Finland
Abstract :
An optimizing automatic code generator for a commercial target signal processor is described. The input to the system is an arbitrary graphical signal flow graph of the application which is converted to a set of linear equations. A number of matrix reduction steps are used to find the optimal order of the computational operations for digital signal processor implementation. This is converted into the assembler code for the TMS320C25 processor
Keywords :
digital signal processing chips; matrix algebra; modules; program assemblers; TMS320C25 processor; arbitrary graphical signal flow graph; assembler code; commercial target signal processor; computational operations; digital signal processor implementation; linear equations; matrix reduction based module optimization; matrix reduction steps; optimizing automatic code generator; Assembly; Delay effects; Digital signal processing; Equations; Flow graphs; Laboratories; Libraries; Optimization methods; Signal generators; Signal processing;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112617
