Real-time parallel processor for on-board airborne synthetic aperture radar (SAR)

A real-time modular architecture that implements an airborne synthetic aperture radar (SAR) processor is described. A high-efficiency computation SAR data-focusing algorithm is used in order to design a scalable architecture able to be adapted to different SAR missions. A multiprocessor digital signal processing (DSP) architecture meets both of the requirements of a high computation throughput, imposed by the real-time focusing algorithm, and of a modular onboard airborne structure. The system design is partitioned into the range-focusing circuit and the azimuth-focusing circuit. While the first stage uses a pipeline structure to interconnect the DSP processors, the azimuth subsystem implements a single input/multiple data structure. This permits an easier growth of processing capabilities and limits the inter-processor communications to a reasonable factor