DocumentCode :
2664239
Title :
Dynamic scheduler for multi-core systems
Author :
Vaidya, Vinay G. ; Ranadive, Priti ; Sah, Sudhakar
Author_Institution :
Centre for Res. in Eng. Sci. & Technol., KPIT Cummins Infosystems Ltd., Pune, India
Volume :
1
fYear :
2010
fDate :
3-5 Oct. 2010
Abstract :
Many dynamic scheduling algorithms have been proposed in the past. With the advent of multi core processors, there is a need to schedule multiple tasks on multiple cores. The scheduling algorithm needs to utilize all the available cores efficiently. The multicore processors may be SMPs or AMPs with shared memory architecture. In this paper, we propose a dynamic scheduling algorithm in which the scheduler resides on all cores of a multi-core processor and accesses a shared Task Data Structure (TDS) to pick up ready-to-execute tasks. This method is unique in the sense that the processor has the onus of picking up tasks whenever it is idle. We have discussed the proposed scheduling algorithm using a set of tasks as an example. The paper concludes with the discussion of advantages and limitations of the proposed scheduling algorithm.
Keywords :
data structures; dynamic scheduling; memory architecture; processor scheduling; shared memory systems; dynamic scheduler; dynamic scheduling algorithm; multicore processor; multicore system; shared memory architecture; shared task data structure; Dynamic scheduling; Heuristic algorithms; Multicore processing; Program processors; Schedules; Scheduling algorithm; Dynamic scheduler; load balancing; multi-core systems; work load distribution;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Software Technology and Engineering (ICSTE), 2010 2nd International Conference on
Conference_Location :
San Juan, PR
Print_ISBN :
978-1-4244-8667-0
Electronic_ISBN :
978-1-4244-8666-3
Type :
conf
DOI :
10.1109/ICSTE.2010.5608969
Filename :
5608969
Link To Document :
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