Title :
A Probabilistic Approach to Diagnose SETs
Author :
Gangadhar, Sreenivas ; Tragoudas, Spyros
Author_Institution :
Dept. of Electr. & Comput. Eng., Southern Illinois Univ. Carbondale, Carbondale, IL, USA
Abstract :
In recent work, the error latching probability due to an SET is calculated for a single observable point, and this help in hardening the design. This paper utilizes a recently proposed probabilistic framework for SET propagation in order to diagnose (on-line or off-line) the location and time of strike based on errors observed at multiple points. The proposed diagnostic framework requires a new approach to calculate the probability for SET propagation to multiple non-independent variables. It is shown experimentally that error appearances at multiple observable points help in SET diagnosis. The time performance of the proposed diagnostic framework is compared against an alternative implementation. This is particularly important in on-line diagnosis.
Keywords :
error statistics; logic circuits; logic design; SET diagnosis; SET propagation probability; error latching probability; nonindependent variables; probabilistic approach; single event transients; Boolean functions; Delay; Equations; Integrated circuit modeling; Logic gates; Mathematical model; Probability; BDD; Boolean difference; SET; diagnosis;
Conference_Titel :
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2011 IEEE International Symposium on
Conference_Location :
Vancouver, BC
Print_ISBN :
978-1-4577-1713-0
DOI :
10.1109/DFT.2011.19