An efficient dual-mode floating-point Multiply-Add Fused Unit

Multiply-Add Fused (MAF) units play a key role in the processor´s performance for a variety of applications. Aiming at improving the MAF functionality this paper presents a dual-mode MAF architecture, which is able to perform either one double-precision or two single-precision operations in parallel. The design attains low latency by following a dual-path approach and by combining final addition with rounding. The organization performs a MAF instruction in three cycles, while single floating-point addition in two cycles. The design has been validated and implemented with TSMC 0.13um.