On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS

This paper presents a detailed characterization of the effects of intra-gate resistive open defects on nanoscaled CMOS gates as causing faults with timing and pattern sequence dependency. The values of the least detectable resistance are established for different feature sizes using HSPICE. It is found that as the feature size is reduced, the value of the least detectable resistance increases in the presence of a fault resulting in a delay of less than one nanosecond. The use of a low voltage testing technique is investigated for the detection of these faults. Finally, an analytical model that takes into account the gate current is proposed, this model considers the pronounced effect of the gate current at a decreasing feature size, while incurring in a small error compared with simulation results.