Title :
A 400 MHz 0.934ps rms jitter multiplying delay lock loop in 90-nm CMOS process
Author :
Chen, Chiou-Bang ; Shih, Homg-Yuan
Author_Institution :
Adv. Mixed-Signal Dept., Ind. Technol. Res. Inst., Hsinchu, Taiwan
Abstract :
A multiplying delay-locked loop (MDLL) is adopted for low-jitter clock generation. This architecture overcomes the drawback of phase-locked loops (PLL) such as jitter accumulation, and maintain the advantage of a PLL for multirate frequency multiplication. The MDLL, implemented in 90-nm CMOS technology, occupies about 1 mm2 and works at 400 MHz with multiplication ratio of 4. The complete synthesizer, including the output buffers, dissipates 31 mW from a 1.2V supply at 400 MHz. The rms jitter is 0.934 ps according to the phase noise integrated from 1 KHz to 1 MHz, when the output frequency is 400 MHz.
Keywords :
CMOS logic circuits; UHF integrated circuits; clocks; delay lock loops; digital phase locked loops; frequency multipliers; frequency synthesizers; integrated circuit noise; low-power electronics; multiplying circuits; phase noise; timing jitter; CMOS process; PLL; frequency 400 MHz; frequency synthesizer; jitter multiplying delay lock loop; low-jitter clock generation; multirate frequency multiplication; phase noise; power 31 mW; size 90 nm; time 0.934 ps; voltage 1.2 V; CMOS integrated circuits; CMOS technology; Gold; Jitter; Low-Jitter; MDLL;
Conference_Titel :
Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on
Conference_Location :
Athens
Print_ISBN :
978-1-4244-8155-2
DOI :
10.1109/ICECS.2010.5724452
