A codebook, distribution and comparator (CDC) chip architecture for real-time image coding

Author

Dezhgosha, K. ; Jamali, M.M. ; Kwatra, S.C.

Author_Institution

Dept. of Electr. Eng., Toledo Univ., OH, USA

fYear

1990

fDate

1-3 May 1990

Firstpage

3034

Abstract

A VLSI architecture for real-time high-quality coding of color TV images at a fixed bit rate of 1.12 BPP is developed. The architecture exploits pipeline/parallel processing an don-chip memory to partition a large codebook into smaller on-chip subcodebooks. The architecture is capable of real-time processing of 480×768 pixels per frame with a refreshing rate of 30 frames/s. A floorplan for the CDC chip is developed

Keywords

VLSI; computerised picture processing; encoding; pipeline processing; real-time systems; video signals; 368640 pixels; 480 pixels; 768 pixels; CDC chip; VLSI architecture; codebook; color TV images; comparator; distribution; fixed bit rate; floorplan; high-quality coding; on-chip memory; pipeline/parallel processing; real-time image coding; refreshing rate; subcodebooks; Computational complexity; Computer architecture; Digital images; Distortion measurement; Encoding; Image coding; Semiconductor device measurement; TV; Vector quantization; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.112651

Filename

112651

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2664573