Title :
On the Delay Analysis of Defective CNTFETs with Undeposited CNTs
Author :
Cho, Geunho ; Lombardi, Fabrizio
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
Abstract :
The Carbon Nano Tube Field Effect Transistor (CNTFET) is a promising device to supersede the MOSFET at the end of the technology roadmap of CMOS. When a CNTFET is fabricated, only some of the CNTs could be deposited. As reported in an earlier paper, this significantly degrades the performance of the CNTFET. In this paper, the delay analysis of a CNTFET in the presence of undeposited CNTs (as defects) is pursued in detail. This analysis considers both the number and the position of the CNT defects and focuses on the impact on delay. A probabilistic delay analysis is also proposed by considering the manufacturing process in this emerging technology, this analysis shows that probabilistically, a substantial performance degradation in delay for a CNTFET exists also at a low number of defective CNTs and such degradation become very severe in the presence of a large number of undeposited CNTs. To reduce the delay degradation, a method based on adjusting the gate width (as applicable using lithography), is proposed. This method considerably reduces the delay degradation (from 43% to 10%).
Keywords :
CMOS integrated circuits; MOSFET; carbon nanotube field effect transistors; probability; C; CMOS roadmap; CNT defects; MOSFET; carbon nanotube field effect transistor; defective CNTFET; delay analysis; delay degradation; manufacturing process; probabilistic delay analysis; undeposited CNT; CNTFETs; Capacitance; Degradation; Delay; Integrated circuit modeling; Logic gates; Probabilistic logic; CNT; CNTFET; Defect modeling; emerging technologies; manufacturing;
Conference_Titel :
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2011 IEEE International Symposium on
Conference_Location :
Vancouver, BC
Print_ISBN :
978-1-4577-1713-0
DOI :
10.1109/DFT.2011.50
