DocumentCode
2664609
Title
On VLSI implementation of median based field rate up-conversion
Author
Juhola, Janne ; Haavisto, Petri ; Vainio, Olli ; Raita-aho, Tommi ; Neuvo, Yrjö
Author_Institution
Signal Process. Lab., Tampere Univ. of Technol., Finland
fYear
1990
fDate
1-3 May 1990
Firstpage
3042
Abstract
Field rate up-conversion using adaptive weighted median filtering is described. The weights of the algorithm are adapted according to the output from a motion detector. High-speed VLSI circuit architectures for the computation of weighted median are discussed. A bit-sliced architecture based on a previously introduced bit-serial method, having good expandability and supporting computation of weighted medians, is described
Keywords
VLSI; bit-slice computers; frequency convertors; VLSI circuit architectures; adaptive weighted median filtering; bit-serial method; bit-sliced architecture; expandability; median based field rate up-conversion; motion detector; weighted median; Adaptive filters; Computer architecture; Filtering; Image converters; Interpolation; Laboratories; Motion compensation; Signal processing; TV; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location
New Orleans, LA
Type
conf
DOI
10.1109/ISCAS.1990.112653
Filename
112653
Link To Document