DocumentCode
2664617
Title
CMOS LNA optimization techniques: Comparative study
Author
Papageorgiou, V. ; Vlassis, S.
Author_Institution
Phys. Dept., Univ. of Patras, Rio, Greece
fYear
2010
fDate
12-15 Dec. 2010
Firstpage
82
Lastpage
85
Abstract
This paper describes and analyzes two low-noise amplifier (LNA) optimization techniques which are applied to the common-source MOS topology with inductive degeneration. The optimization techniques are consisted of the inductive-specified and the current-specified technique. The purpose of the paper is to provide clear understanding of the design guidelines, limitations and the pros and cons regarding each design technique. LNA examples are designed following the guidelines of each technique using standard CMOS 0.18um process.
Keywords
CMOS analogue integrated circuits; integrated circuit design; low noise amplifiers; optimisation; CMOS process; common-source MOS topology; comparative study; current-specified technique; inductive degeneration; inductive-specified technique; low-noise amplifier optimization technique; size 0.18 mum; CMOS LNA; LNA optimization techniques; inductive degeneration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on
Conference_Location
Athens
Print_ISBN
978-1-4244-8155-2
Type
conf
DOI
10.1109/ICECS.2010.5724459
Filename
5724459
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