DocumentCode
2664625
Title
A 65 MHz 16-tap FIR filter chip with on-chip video delay lines
Author
Rao, Sailesh K. ; Hatamian, Mehdi
Author_Institution
AT&T Bell Lab., Holmdel, NJ, USA
fYear
1990
fDate
1-3 May 1990
Firstpage
3050
Abstract
The VLSI design of a 16-tap finite impulse response (FIR) filter chip with programmable line delays for video applications is described. The chip is fabricated in 0.9-μm CMOS technology. It is tested at sample rates up to 65 MHz. The chip contains about 600000 devices in less than 22 mm2 of silicon area
Keywords
CMOS integrated circuits; VLSI; digital filters; video signals; 0.9 micron; 16-tap FIR filter chip; CMOS technology; VLSI design; finite impulse response; on-chip video delay lines; programmable line delays; sample rates; silicon area; CMOS technology; Delay lines; Digital signal processing chips; Finite impulse response filter; Hardware; Signal processing algorithms; Silicon; Testing; Very large scale integration; Video signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location
New Orleans, LA
Type
conf
DOI
10.1109/ISCAS.1990.112655
Filename
112655
Link To Document