DocumentCode
2664732
Title
Duplicated Execution Method for NoC-based Multiple Processor Systems with Restricted Private Memories
Author
Imai, Masashi ; Yoneda, Tomohiro
Author_Institution
Univ. of Tokyo, Tokyo, Japan
fYear
2011
fDate
3-5 Oct. 2011
Firstpage
463
Lastpage
471
Abstract
We propose a processor-level fault tolerance technique based on the Pair and Swap scheme to improve the dependability of network-on-chip based multiple processor systems where each processor core has its private memory. In the proposed scheme, two identical copies of a given task are executed on a pair of processor cores and the results are compared repeatedly in order to detect processor faults. We propose that each task is quadruplicated and statically assigned to private memories so that each memory has only two different tasks. We evaluate the reliability of the proposed quadruplicated task allocation method in the viewpoint of MTTF (Mean Time To Failure). As a result, the MTTF of the proposed method is over 4.3 times longer than that of the duplicated task allocation method.
Keywords
circuit reliability; fault tolerance; network-on-chip; MTTF; NoC-based multiple processor systems; duplicated execution method; mean time to failure; network-on-chip; pair scheme; private memory; processor core; processor-level fault tolerance technique; quadruplicated task allocation method; reliability; restricted private memories; swap scheme; Computer architecture; Fault tolerance; Fault tolerant systems; Instruction sets; Resource management; System-on-a-chip; Transient analysis; Dependability; Fault diagnosis; MTTF; Multiple processor system; Network-on-Chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2011 IEEE International Symposium on
Conference_Location
Vancouver, BC
Print_ISBN
978-1-4577-1713-0
Type
conf
DOI
10.1109/DFT.2011.38
Filename
6104475
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