• DocumentCode
    2664750
  • Title

    Route-Aware Task Mapping Method for Fault-Tolerant 2D-Mesh Network-on-Chips

  • Author

    Kutami, H. ; Fukushima, Yasuhiro ; Fukushi, Masaru ; Yairi, Ikuko Eguchi ; Hattori, Toshihiro

  • Author_Institution
    Fac. of Sci. & Technol., Sophia Univ., Tokyo, Japan
  • fYear
    2011
  • fDate
    3-5 Oct. 2011
  • Firstpage
    472
  • Lastpage
    480
  • Abstract
    This paper deals with the issue of task mapping onto fault-tolerant 2D-Mesh Network-on-Chips (2D-MNoCs). In the fault-tolerant 2D-MNoCs, fault-tolerant deadlock-free routing control without assistance of hardware (such as lookup table and virtual channel) is desirable due to simple router architecture, low power consumption and easy fault diagnosis. For such fault-tolerant 2D-MNoCs, existing task mapping methods are not efficient because task assignment process and route decision process, which are closely interdependent, are performed separately. In this paper, we propose a new route-aware task mapping method based on a generic algorithm. Our method considers the effect of overlapped routing paths provided by a fault-tolerant routing control in assigning tasks to nodes and obtains a quasi-optimal solution by the genetic algorithm. Experimental study compares overall performances of our method with a random mapping method under the random and cluster fault models, and shows that our method consistently leads to reduction in the total execution time of mapped applications.
  • Keywords
    fault diagnosis; fault tolerance; genetic algorithms; network routing; network-on-chip; 2D-MNoC; fault diagnosis; fault-tolerant 2D-mesh network-on-chips; fault-tolerant deadlock-free routing control; genetic algorithm; low power consumption; route-aware task mapping method; simple router architecture; Biological cells; Circuit faults; Delay; Fault tolerance; Fault tolerant systems; Routing; System recovery; Task mapping; fault-tolerant routing control algorithm; genetic algorithm; two-dimensional mesh-based network-on-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2011 IEEE International Symposium on
  • Conference_Location
    Vancouver, BC
  • Print_ISBN
    978-1-4577-1713-0
  • Type

    conf

  • DOI
    10.1109/DFT.2011.61
  • Filename
    6104476