Title :
Synthesis for testability: a brief survey
Author :
Devadas, Srinivas ; Keutzer, Kurt
Author_Institution :
MIT, Cambridge, MA, USA
Abstract :
Previously published work in the synthesis and testing areas is briefly surveyed and critically discussed. Synthesis for testability for both combinational logic and sequential circuits is discussed
Keywords :
combinatorial circuits; logic design; logic testing; sequential circuits; combinational logic; design for testability; sequential circuits; synthesis for testability; testing; Adders; Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Delay; Logic testing; Redundancy; Robustness; Sufficient conditions;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112667
