Title :
Multiple fault testable sequential circuits
Author :
Ashar, Pranav ; Devadas, Srinivas ; Newton, A. Richard
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
The effects of multiple stuck-at faults on sequential circuits are analyzed. It is shown that the effects of multiple stuck-at faults on the state graph of a sequential circuit can be much more dramatic than the effects of single stuck-at faults. Methods for the synthesis of sequential circuits for high multiple fault testability are proposed
Keywords :
logic design; logic testing; sequential circuits; multiple fault testability; multiple stuck-at faults; state graph; testable sequential circuits; Circuit faults; Circuit synthesis; Circuit testing; Encoding; Fault detection; Logic; Redundancy; Sequential analysis; Sequential circuits; Tiles;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112672
