Optimum DSP multiprocessor architecture for efficient execution of the fast transversal filter

The design and development of an efficient multiprocessor system to implement the fast transversal filter (FTF) using commercially available digital signal processors (DSPs) is presented. The system is designed with some flexibility in it to be able to run other commonly used adaptive signal-processing algorithms. The FTF algorithm is analyzed, noting sequential characteristics and heavy computational bottlenecks that limit the speed at which the algorithm runs. The algorithm is speared to couple of data independent partitions which were data dependent by data flow concept. Parallelisms within the FTF and within its vector computations are the target of speedup efforts. The design is chosen to maximize speedup and minimize interprocessor communication, all with the minimum number of processors and simplest control logic. A prototype of the system using four Motorola DSP56001 fixed-point DSPs is discussed. The system has a speedup factor of nearly 4 over the single-DSP implementations