Sub-THz high gain wide-band low noise amplifiers in 90nm RF CMOS technology

In the future, CMOS technology is expected to enable low-cost sub-THz applications such as high data-rate communication links, passive and active imaging and sensor systems, and instrumentation and measurements equipment. This paper presents key design techniques for different CMOS LNA topologies with over 20 GHz bandwidth ranging from 90 GHz to 110 GHz. The proposed LNA topologies are, the three-stage cascode RF NMOS configuration and four-stage Common Gate followed by Common Source configuration. Simulation results show that the first topology can achieve a peak gain of 23.5 dB at 92.1 GHz with a 3-dB bandwidth of 25 GHz, and a noise figure less than 5.5 dB over the entire bandwidth. The achieved peak gain from the second topology is 23.2 dB at 105 GHz with a 3-dB bandwidth of 15 GHz and a noise figure less than 6.1 dB over the entire bandwidth. The LNAs are designed in 90 nm RF CMOS and consume 27 mW/40 mW for topology I/topology II respectively.