Higher density using diffusion patterned vias and fine line printing

Design guidelines, process steps and test results from fabrication of two 40-mm multichip module (MCM)-Cs using the latest thick materials and printing techniques are discussed. Two two LIC (line interface controller) modules are designed with two large ASICs (plus memory) and prototyped using thick film gold conductors with 3 mil line/space and 6 mil via criteria. The second prototype of the LIC module utilizes silver conductors at 5 mil line and gap to further reduce cost. The second module design uses more bare die (field programmable gate arrays and memory) for a much higher interconnect density but still uses existing design guidelines. It is believed that 4 mil vias can be achieved in production and will be developed for future designs require higher density. Diffusion patterning allows a 50% reduction (4-6 mil) in via size versus traditional printed vias (10-20 mil)