Low Cost Concurrent Error Detection for On-Chip Memory Based Embedded Processors

This paper proposes an efficient concurrent error detection method using control flow checking for embedded processors. The proposed method is based on the co-operation of two hardware modules: 1) an on-chip hardware component to detect branch instructions and generate signatures for the running program, and 2) an external watchdog processor to compare runtime signatures and branch addresses with the information extracted offline. The proposed method is implemented on an embedded processor core and is evaluated by a simulation based statistical fault injection approach where faults are injected into cache and main memory. Experimental results show that the proposed method detects more than 96.7% of all errors with only 2.6% overhead in area and less than 1% increase in power consumption. Furthermore, this technique imposes almost no performance degradation.