Title :
A generic tolerance analysis model with illustrations for TAB bonding
Author :
Banerjee, Koushik ; Natarajan, Siva ; Connor, Bill ; Wittrock, Janice
Author_Institution :
Intel Corp., Chandler, AZ, USA
Abstract :
From first principles a generic model which can be applied to a variety of problems associated with placement errors, which are not limited to overlapping features alone is generated. The same model with minor changes is used to predict what the tolerances on a die and bond stage should be, such that the die edge does not interfere with the edges of the cavity of the bond stage when it is placed in the stage. The model is verified with actual data, and proves to be quite accurate
Keywords :
circuit layout; covariance analysis; tape automated bonding; tolerance analysis; TAB; alignment problems; design parameters; generic tolerance analysis model; inner lead bonding; normality assumption; outer lead bonding; placement errors; statistical variance component analysis; Analysis of variance; Bonding; Computer aided software engineering; Lead; Manufacturing processes; Predictive models; Semiconductor device modeling; Synthetic aperture sonar; Tolerance analysis; Virtual manufacturing;
Conference_Titel :
Electronic Manufacturing Technology Symposium, 1993, Fifteenth IEEE/CHMT International
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-1424-7
DOI :
10.1109/IEMT.1993.398180
